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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85314-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
FEATURES
* 5 differential 2.5V/3.3V LVPECL outputs * Selectable differential CLK0, nCLK0 or LVCMOS inputs * CLK0, nCLK0 pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * CLK1 can accept the following input levels: LVCMOS or LVTTL * Maximum output frequency: 650MHz * Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input * Output skew: 50ps (maximum) * Part-to-part skew: 400ps (maximum) * Propagation delay: CLK0, nCLK0 - 2.1ns (maximum) CLK1 - 2.1ns (maximum) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V * -40C to 85C ambient operating temperature * Compatible to part number MC100LVEL14
GENERAL DESCRIPTION
The ICS85314-01 is a low skew, high performance 1-to-5 Differential-to-3.3V LVPECL fanout buffer HiPerClockSTM and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS85314-01 has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
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Guaranteed output and part-to-part skew characteristics make the ICS85314-01 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
nCLK_EN D Q LE CLK0 nCLK0 CLK1
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC nCLK_EN VCC nc CLK1 CLK0 nCLK0 nc CLK_SEL VEE
00 1
1
Q0 nQ0 Q1 nQ1
CLK_SEL Q2 nQ2 Q3 nQ3 Q4 nQ4
ICS85314-01
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm Package Body G Package Top View
ICS85314-01
20-Lead SOIC 7.5mm x 12.8mm x 2.3mm Package Body M Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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REV. B JUNE 21, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85314-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Type Description Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Negative supply pin. Clock select input. When HIGH, selects SCLK input. Pulldown When LOW, selects CLK, nCLK inputs. LVTTL / LVCMOS interface levels. No connect. Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Pulldown Clock input. LVTTL / LVCMOS interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 8 9, 10 11 12 13, 17 14 15 16 18, 20 Name Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3 Q4, nQ4 VEE CLK_SEL nc nCLK0 CLK0 CLK1 VCC Output Output Output Output Output Power Input Unused Input Input Input Power
Positive supply pins. Synchronizing clock enable. When LOW, clock outputs follow clock 19 nCLK_EN Input Pulldown input. When HIGH, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
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REV. B JUNE 21, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85314-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Inputs Outputs Selected Source CLK0, nCLK0 CLK1 CLK0, nCLK0 Q0:Q4 Enabled Enabled Disabled; LOW nQ0:nQ4 Enabled Enabled Disabled; HIGH
TABLE 3A. CONTROL INPUT FUNCTION TABLE
nCLK_EN 0 0 1 CLK_SEL 0 1 0
1 1 CLK1 Disabled; LOW Disabled; HIGH After nCLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1 inputs as described in Table 3B.
Disabled
nCLK0 CLK0, CLK1
Enabled
nCLK_EN
nQ0:nQ4 Q0:Q4
FIGURE 1 - nCLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK0 or CLK1 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK0 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q4 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ4 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
85314AG-01
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REV. B JUNE 21, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85314-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
4.6V -0.5V to VCC + 0.5V -0.5V to VCC + 0.5V 73.2C/W (0 lfpm) -65C to 150C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCCx Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40C TO 85C
Symbol VCC IEE Parameter Power Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 55 Maximum 3.8 Units V mA
TABLE 4B. LVCMOS / LVTTL CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current nCLK_EN, CLK_SEL CLK1 nCLK_EN, CLK_SEL CLK1 CLK1, CLK_SEL, nCLK_EN CLK1, CLK_SEL, nCLK_EN Test Conditions Minimum 2 2 -0.3 -0.3 VIN = VCC = 3.8V VCC = 3.8V, VIN = 0V -5 Typical Maximum VCC + 0.3 VCC + 0.3 0.8 1.3 150 Units V V V V A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK0 CLK0 nCLK0 CLK0 Test Conditions VCC = VIN = 3.8V VCC = VIN = 3.8V VCC = 3.8V, VIN = 0V VCC = 3.8V, VIN = 0V -150 -5 1.3 VCC - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR 0.5 NOTE 1, 2 NOTE 1: For single ended applications the maximum input voltage for CLK0, nCLK0 is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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REV. B JUNE 21, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85314-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 1.0 VCC - 1.7 1.0 Units V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40C TO 85C
Symbol Parameter VOH VOL VSWING Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40C TO 85C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay, Low to High CLK0, nCLK0; NOTE 1 CLK1; NOTE 2 650MHz 250MHz 1.0 1.0 Test Conditions Minimum Typical Maximum Units 650 2.1 2.1 50 400 20% to 80% @ 50MHz 20% to 80% @ 50MHz CLK0, nCLK0 650MHz 200 200 45 700 700 55 55 MHz ns ns ps ps ps ps % %
t sk(o) t sk(pp)
tR tF odc
Output Skew; NOTE 3, 5 Par t-to-Par t Skew; NOTE 4, 5 Output Rise Time Output Fall Time Output Duty Cycle
CLK1 250MHz 45 All parameters measured at 250MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Measured from VCC/2 input crossing point to the differential output crossing point. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
85314AG-01
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REV. B JUNE 21, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85314-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VCC
SCOPE
Qx
LVPECL
VCC = 2V
nQx
VEE = -1.8V to -0.375V
OUTPUT LOAD TEST CIRCUIT
VCC
nCLK V CLK
PP
Cross Points
V
CMR
VEE
DIFFERENTIAL INPUT LEVEL
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REV. B JUNE 21, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85314-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
nQx Qx
nQy
Qy
tsk(o)
OUTPUT SKEW
nCLK
CLK
nQ0:nQ4 Q0:Q4
t
PD
PROPAGATION DELAY (DIFFERENTIAL INPUT)
V
SCLK
CC
2
nQ0:nQ4 Q0:Q4
t
PD
PROPAGATION DELAY (LVCMOS INPUT)
85314AG-01
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REV. B JUNE 21, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85314-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
80% 80% V 20% 20% t t
SWING
Clock Inputs and Outputs
R
F
INPUT
AND
OUTPUT RISE
AND
FALL TIME
nQ0:nQ4 Q0:Q4
Pulse Width t t odc = t
PW PERIOD
PERIOD
odc & tPERIOD
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REV. B JUNE 21, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85314-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K CLK_IN + V_REF
-
C1 0.1uF R2 1K
FIGURE 2 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
Zo = 50 5 2 Zo FOUT FIN Zo = 50 Zo = 50 50 50 VCC - 2V
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V 5 2 Zo
FOUT
FIN
RTT =
1 (VOH + VOL / VCC -2) -2
Zo
FIGURE 3A - LVPECL OUTPUT TERMINATION
85314AG-01
RTT
Zo = 50 3 2 Zo 3 2 Zo
FIGURE 3B - LVPECL OUTPUT TERMINATION
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85314-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85314-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS85314-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 55mA = 209mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power_MAX (3.465V, with all outputs switching) = 209mW + 151mW = 360mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.360W * 66.6C/W = 109C. This is well below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE qJA
FOR
20-PIN TSSOP, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5C/W 98.0C/W 88.0C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2C/W 66.6C/W 63.5C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6B. THERMAL RESISTANCE qJA
FOR
20-PIN SOIC, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 83.2C/W 65.7C/W 57.5C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2C/W 39.7C/W 36.8C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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PRELIMINARY
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 4.
ICS85314-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 4 - LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CC_MAX
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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REV. B JUNE 21, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85314-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7A. JAVS. AIR FLOW TABLE FOR TSSOP
q by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7B. JAVS. AIR FLOW TABLE
FOR
SOIC
q by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2C/W 46.2C/W
200
65.7C/W 39.7C/W
500
57.5C/W 36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85314-01 is: 674
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REV. B JUNE 21, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85314-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
PACKAGE OUTLINE - G SUFFIX
TABLE 8A. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 Millimeters Minimum 20 1.20 0.15 1.05 0.30 0.20 6.60 Maximum
Reference Document: JEDEC Publication 95, MO-153 www.icst.com/products/hiperclocks.html
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85314AG-01
REV. B JUNE 21, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85314-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX
TABLE 8B. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 12.60 7.40 1.27 BASIC 10.65 0.75 1.27 8 Millimeters Minimum 20 2.65 -2.55 0.51 0.32 13.00 7.60 Maximum
Reference Document: JEDEC Publication 95, MS-013, MO-119
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REV. B JUNE 21, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85314-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Marking Package 20 lead TSSOP 20 lead TSSOP on Tape and Reel 20 lead SOIC 20 lead SOIC on Tape and Reel Count 72 per tube 2500 38 per tube 1000 Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS85314AG-01 ICS85314AG-01T ICS85314AM-01 ICS85314AM-01T ICS85314AG01 ICS85314AG01 ICS85314AM01 ICS85314AM01
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85314AG-01
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